CEC470 Computer Architectures Fall 2009

Logisitics:

Instructor:Dr. M.S. Jaffe    

Office:                  KEC142
Office Hours:      TBD
 

Integrity Policy: Please read my notes on the standards I'll enforce for student integrity; you will be held to these standards whether you read my notes or not.   
 
Disability Accomodation:  ERAU is committed to the success of all students. It is a University policy to provide reasonable accommodations to students with disabilities. If you would like to request accommodations due to a physical, mental, or learning disability, please contact the Disability Support Service department in Building 18 or call 777-3700. All discussions are confidential.
 

Location and Time:	KEC131, TTh 12 - 1:15
Textbook:	Hennessy and Patterson, Computer Architecture:  A Quantitative Approach, 3rd edition, which is out of print but still available online. The 4th edition deleted a chapter that I really liked; hence my wish to use the 3rd edition.
Prerequisites:	CEC320 or equivalent (no exceptions --- you wouldn't want to try; trust me)

Goals/Objectives:  Understand (and, I hope, enjoy the engineering aesthetics of) the organization of modern computers, with particular emphasis on architectural techniques used to speed up their performance — it's not all just clock speed, folks, not by a long shot.  For each architectural feature, we'll discuss:

• Applicability/assumptions
• Advantages
• Limitations

Announcements:  Announcements for this class (midterm dates, homework assignments, etc.) will be posted on the ERAU BlackBoard site.

Attendance:  Classroom attendance is strongly recommended; the textbook is  good but I put my own slant and perspective on this material and the exams will cover what I think is important.

Overview:  The course will cover Chapters 1, 2, 5, and Appendix A of the text. ((These are long chapters, folks.)  The material in Appendix A used to be in Chapters 3 and 4 in an earlier edition of this text. I like that material a lot and don't think you've seen it elsewhere; hence my inclusion of Appendix A as a main part of this course.   We're basically interested in five subjects: 

1. What is an "instruction set architecture" and what are the major alternatives in designing one?
2. What determines the speed of a computer and how is it really to be measured and compared quantitatively?  What are the limiting factors?
   
3. How can we speed up the CPU beyond the "raw" clock speed limitations?  
4. How can we speed up the memory? 
5. How can we speed up the interconnection of the memory and the processing elements?

Grading:

• 2 midterms @ 25 percent each
    
• Cumulative final exam (but heaviest on the last third of the course) @ 50%.  
    
• All 3 exams will will feature both quantitative and conceptual questions (e.g., define and then compare and contrast sector mapping versus fully associative cache).  Quantitative questions will be very similar to the homework (see below).  I grade on a curve so that a difficult exam should not be a cause for panic.  If the curve is tight, I'll be perfectly happy to give all A's and B's (or even, in theory, all A's).  But I can and will (and usually do) give lower grades to students significantly below the class average.
  

Homework:  I'll recommend problems at the back of each chapter but will not grade them.  (You can always come to me for help, however.)  But the quantitative portion of the exams will follow the recommended problems very closely — if you do the problems, the exams will be easy.  If you don't; they won't.